esp32sim is an open-source, MIT-licensed emulator written in Rust that performs instruction-level emulation of four Espressif ESP32 system-on-chips: the classic ESP32, the ESP32-S3 (dual-core Xtensa LX7), the ESP32-C3 (single-core RISC-V RV32IMC), and the ESP32-C6 (single-core RISC-V RV32IMAC). Each target boots the real mask ROM, the real second-stage bootloader, and an unmodified application image — no patched firmware, no stubs. The S3 variant is considered mature; the C3 and C6 are marked draft. The decoder verification numbers are striking. The Xtensa LX7 decoder has been checked against 977,000 instructions with zero mismatches. The C3 RISC-V decoder reports 161,000 instructions with zero mismatches; the C6, 126,000 with zero mismatches. Hardware-level validation against physical boards shows 205 of 208 console lines identical for the C3 over three boot cycles and 203 of 204 for the C6. These are not synthetic benchmarks — they are line-for-line comparisons against real silicon. Performance on the S3 path uses a block interpreter plus an AArch64 JIT, reaching 150–240 million emulated instructions per second — roughly 30× faster than real-time execution of a helloworld example. The RISC-V targets use a plain interpreter without JIT and still exceed real-time speeds. All three architectures compile to WebAssembly and run in a browser with no installation required. The peripheral model is deep enough to matter. Virtual WiFi provides a full AP with WPA2, DHCP, DNS, NTP, and NAT to the host network — including HTTPS. Board models emit pin-level events (GPIO edges, RMT symbol streams, I2S audio samples) and support specific hardware targets: the LilyGO TTGO T-Display, the Waveshare ESP32-S3-Touch-LCD-4B with its 480×480 touchscreen, and the Waveshare ESP32-S3-CAM-OV5640 with camera, codecs, and pedestrian detection running on the emulated PIE SIMD unit. Display drivers include ST7735, ST7789, ST7701S, and CO5300. The architecture is modular. A shared emu-core crate provides the Bus and Core traits used by both CPU families. esp-periph houses the peripheral IP (UART, systimer, GPIO, SPI, GDMA, crypto, I2S, RMT, I2C) shared across chips. Each SoC plugs in its own memory map, cache controller, and interrupt routing. Adding a new board means implementing a trait. The C3 reuses the S3's UART, USB-Serial/JTAG, systimer, timer groups, GPIO, SPI flash controller, GDMA, and SHA/AES/RSA models unchanged; the C6 reuses those same models with its own PLIC, L1 cache, and LP blocks. The structural significance here is the elimination of a hardware dependency from the embedded development loop. Firmware developers can iterate, test, and debug without physical boards, JTAG probes, or cloud-hosted emulation services. CI pipelines can run golden-output regression tests against emulated firmware. The browser target means onboarding and education require nothing more than a URL. No accounts, no subscriptions, no vendor lock-in. This is a genuinely generative contribution to the ESP32 ecosystem. It reduces the cost of entry for firmware development, enables testing at scale, and does so under MIT with full source. The 'no cloud, no accounts' positioning is a direct rejection of the SaaS-ification of developer tooling. The limiting factor is maturity: the S3 path is production-grade, but the RISC-V targets are draft, and peripheral coverage will need to grow to match the full breadth of real-world ESP32 projects.
